Issue 1 | arXiv quant-ph, 20 October 2026

Conveyor belts for qubits: a blueprint for fast, low-overhead error correction in silicon

Our understanding

Slide 1: Conveyor belts for qubits. Status: design and simulation, a blueprint for fast error correction on silicon chips, nothing built. A large loop of 24 blue qubits around two smaller loops of 12 white qubits each, like conveyor belts inside a conveyor belt.Slide 2: The most efficient codes link far-apart qubits. A grid of 28 qubits in 4 rows of 7; three long orange arcs labelled checks across the chip connect qubits far apart, their end qubits shown in blue.Slide 3: In silicon, qubits can ride on tracks. Two loops of qubits moving in opposite directions; where they touch, two blue qubits meet, labelled partners meet.Slide 4: 1,400 code qubits carry 280 logical ones. The largest code from the search, [[1400, 280, at most 28]], rate 20 percent, distance only bounded at 28 or less. A block of 1,400 grey dots with an arrow to a block of 280 blue dots.Slide 5: One round of checks in under 50 microseconds. Log-scale time line with steps of ten: 50 microseconds, 500 microseconds, 5 milliseconds, 50 milliseconds. NeST marked below 50 microseconds; neutral atoms shown as a range from 5 to 50 milliseconds, placed from the paper’s factor of 100 to 1,000.Slide 6: A blueprint, not a chip. The headline estimate of 10 to the minus 14 logical errors per qubit and round assumes shuttling ten times better than early demonstrations. A log-scale shuttling-error line with a grey point for early demos and an orange point for the assumed value, one step of ten better. Link to anyon.news.
Slide 1 of 6

Some of the most efficient ways to protect quantum information need qubits that sit far apart to compare notes. In silicon chips, qubits can be moved quickly, but only along fixed tracks. This design lays the tracks out as conveyor belts inside conveyor belts, so whole rows of qubits move together and meet the right partners. In simulations, one full round of checks takes less than 50 millionths of a second, hundreds to thousands of times faster than with neutral atoms. It is a blueprint. Nothing has been built yet.

The details

Figure 1 of the paper: (a) a lifted product code laid out on the NeST architecture, with qubit loops and shuttling tracks; (b) one unit cell that mirrors the base group of the code.
Figure 1 of Siegel, arXiv:2610.28538, CC BY 4.0. Unmodified.

What they did

Quantum low-density parity-check (qLDPC) codes can protect many logical qubits with few physical ones, encoding rates up to 50 % at useful distances, but their checks connect qubits that are far apart; so far only neutral-atom machines have supplied that connectivity. The paper proposes doing it with silicon spin qubits, which can be shuttled along fabricated tracks in microseconds rather than milliseconds, but only along fixed paths without collisions. The design, NeST (Nested Shuttling Tracks), arranges nested conveyor-belt loops on a square lattice so that every required permutation becomes a rigid, globally controlled motion of whole trains of qubits. A code search finds rate-20 % codes up to [[1400, 280, ≤ 28]]; circuit-level simulations including shuttling dephasing give thresholds above 10⁻³ with stabiliser cycles under 50 μs, two to three orders of magnitude faster than neutral-atom implementations. For a [[150, 30, 10]] code the author builds a code-surgery gadget with no extra qubits and 29 % more gate layers.

Why it matters

It is the first co-design of a qLDPC code family and spin-qubit hardware, according to the author, and it argues that very low overhead and a fast clock need not be traded against each other. All of this is design and simulation; nothing has been built.

What is still open

The headline logical error estimate (10⁻¹⁴ per qubit per round) assumes a ten-fold improvement over early shuttling demonstrations and other errors at 0.1 %. Which assumption is closer to today’s silicon devices, and what happens to the thresholds if shuttling stays where it is? (our inference)

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